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1 datasheet 7.5v radiation hardened ultra low noise, precision voltage reference isl71090seh75 the isl71090seh75 is an ultra low noise, high dc accuracy precision voltage reference with a wide input voltage range from 9.2v to 30v. the isl71090seh75 uses the intersil advanced bipolar technology to achieve 1.0v p-p noise at 0.1hz with an accuracy over temperature of 0.15%. the isl71090seh75 offers a 7.5v output voltage with 10ppm/c temperature coefficient and also provides excellent line and load regulation . the device is offered in an 8 ld flatpack package. the isl71090seh75 is ideal fo r high-end instrumentation, data acquisition and applications requiring high dc precision where low noise performance is critical. applications ? rh voltage regulators precision outputs ? precision voltage sources for data acquisition system for space applications ? strain and pressure gaug e for space applications features ? reference output voltage . . . . . . . . . . . . . . . . . . 7.5v 0.05% ? accuracy over temperature . . . . . . . . . . . . . . . . . . . . . 0.15% ? output voltage noise . . . . . . . . .1.0v p-p typ (0.1hz to 10hz) ? supply current . . . . . . . . . . . . . . . . . . . . . . . . . . . . 930a (typ) ? tempco (box method) . . . . . . . . . . . . . . . . . . . 10ppm/c max ? output current capability . . . . . . . . . . . . . . . . . . . . . . . . 20ma ? line regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8ppm/v ? load regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . .10ppm/ma ? operating temperature range. . . . . . . . . . . .-55c to +125c ? radiation environment - high dose rate (50-300rad(si)/s) . . . . . . . . . . . 100krad(si) - low dose rate (0.01rad(si)/s) . . . . . . . . . . . . . 100krad(si)* - set/sel/seb . . . . . . . . . . . . . . . . . . . . . . 86mev?cm 2 /mg *product capability established by initial characterization. the ?eh? version is acceptance tested on a wafer-by-wafer basis to 50krad(si) at low dose rate ? electrically screened to smd 5962-13211 related literature ? an1847 , ?isl71090seh12ev1z, isl71090seh25ev1z, isl71090seh50ev1z, isl71090seh75ev1z user guide? ? an1848 , ?single event effects (see) testing of the isl71090seh precision voltage reference? ? an1849 , ?total dose testing of the isl71090seh precision voltage reference? figure 1. isl71090seh75 typical application diagram figure 2. v out vs temperature 0.1f vee vdd refin vdd bipoff vee dacout gnd vin vref 1f d0 hs-565brh 1 2 3 4 6 8 7 5 isl71090seh75 d12 1.1k c note: select c to minimize settling time. dnc vin comp gnd dnc dnc vout trim 1nf 7.490 7.492 7.494 7.496 7.498 7.500 7.502 7.504 7.506 7.508 7.510 -80 -60 -40 -20 0 20 40 60 80 100 120 140 temperature (c) 7.5v + 0.1% 7.5v - 0.1% unit 1 unit 4 unit 5 unit 2 unit 3 v out (v) march 18, 2016 fn8591.3 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas llc 2013, 2016. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners.
isl71090seh75 2 fn8591.3 march 18, 2016 submit document feedback ordering information ordering number ( notes 1 , 2 )part number v out option (v) temp range (c) package (rohs compliant) pkg. dwg. # 5962r1321104vxc isl71090sehvf75 7.5 -55 to +125 8 ld flatpack k8.a isl71090sehf75/proto isl71090sehf75/proto 7.5 -55 to +125 8 ld flatpack k8.a 5962r1321104v9a isl71090sehvx75 7.5 -55 to +125 die ISL71090SEHX75SAMPLE ISL71090SEHX75SAMPLE 7.5 -55 to +125 die isl71090seh75ev1z evaluation board notes: 1. these intersil pb-free hermetic packaged products employ 100% au plate - e4 termination finish, which is rohs compliant and c ompatible with both snpb and pb-free soldering operations. 2. specifications for rad hard qml devices are controlled by the defense logistics agency land and maritime (dla). the smd numbe rs listed in this ?ordering information? table must be used when ordering. table 1. key differences between family of parts part number v out (v) tempco (ppm/c) output voltage noise (v p-p) load regulation (ppm/ma) isl71090seh12 1.25 10 1 35 isl71090seh25 2.5 10 2 2.5 isl71090seh50 5.0 10 1.1 10 isl71090seh75 7.5 10 1 10
isl71090seh75 3 fn8591.3 march 18, 2016 submit document feedback pin configuration isl71090seh75 (8 ld flatpack) top view 8 7 6 5 2 3 4 1 dnc vin comp gnd dnc dnc vout trim note: the esd triangular mark is indicative of pi n #1. it is a part of the device marking and is placed on the lid in the quadrant where pin #1 is located. pin descriptions pin number pin name esd circuit description 1, 7, 8 dnc 3 do not connect. internally terminated. 2 vin 1 input voltage connection 3 comp 2 compensation and noise reduction capacitor 4 gnd 1 ground connection. also connected to the lid. 5 trim 2 voltage reference trim input 6vout2voltage reference output vdd capacitively triggered clamp gnd vdd gnd pin esd circuit 1 esd circuit 2 esd circuit 3 vdd dnc
isl71090seh75 4 fn8591.3 march 18, 2016 submit document feedback functional block diagram figure 3. functional block diagram comp gnd vout trim dnc dnc dnc band gap reference bias regulator vin gm 1.2v 1.2v 3.7v
isl71090seh75 5 fn8591.3 march 18, 2016 submit document feedback absolute maximum rating s thermal information maximum voltage v in to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to +40v v in to gnd at an let = 86mev ? cm 2 /mg . . . . . . . . . . . . . . -0.5v to +36v v out to gnd (10s). . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5v to v out + 0.5v voltage on any pin to ground . . . . . . . . . . . . . . . . . -0.5v to +v out + 0.5v voltage on dnc pins . . . . . . . . . . . . no connections permitted to these pins esd ratings human body model (tested per mil-prf-883 3015.7). . . . . . . . . . . 2kv machine model (tested per jesd22-a115-a) . . . . . . . . . . . . . . . . . . 200v charged device model (tested per jesd22-c101d) . . . . . . . . . . . 750v thermal resistance (typical) ? ja (c/w) ? jc (c/w) 8 ld flatpack package ( notes 3 , 4 ). . . . . . 140 15 storage temperature range. . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c maximum junction temperature (t jmax ). . . . . . . . . . . . . . . . . . . . . .+150c recommended operating conditions v in . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.2v to +30v temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55c to +125c caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 3. ? ja is measured with the component mounted on a high effective thermal conductivity test board in free air. see tech brief tb379 for details. 4. for ? jc , the "case temp" location is the center of the ceramic on the package underside. 5. product capability established by initial characterization. the "eh" version is accept ance tested on a wafer-by-wafer basis t o 50krad(si) at low dose rate. 6. the output capacitance used for see testing is c in = 0.1f and c out = 1f. electrical specific ations for flatpack v in = 15v, i out = 0ma, c l = 0.1f and c c = 1nf unless otherwise specified. boldface limits apply after radiation a t +25c and across the operating temperature range, -55c to +125c without radiation, unless otherwise specified. parameter description test conditions min ( note 7 )typ max ( note 7 )unit v out output voltage 7.5 v v oa v out accuracy at t a = +25c v out = 7.5v, ( note 9 ) -0.05 +0.05 % v out accuracy at t a = -55c to +125c v out = 7.5v, ( note 9 ) -0.15 +0.15 % v out accuracy at t a = +25c, post radiation v out = 7.5v, ( note 9 ) -0.3 +0.3 % tc v out output voltage temperature coefficient ( note 8 ) 10 ppm/c v in input voltage range 9.2 30 v i in supply current 0.930 1.500 ma ? v out / ? v in line regulation v in = 9.2v to 30v 8 20 ppm/v ? v out / ? i out load regulation sourcing: 0ma i out 20ma 10 20 ppm/ma sinking: -10ma i out 0ma 21 40 ppm/ma v d dropout voltage ( note 10 )1.5 1.7 v i sc+ short-circuit current t a = +25c, v out tied to gnd 53 ma i sc- short-circuit current t a = +25c, v out tied to v in -63 ma t r turn-on settling time 90% of final value, c l = 1.0f, c c = open 250 s psrr ripple rejection f = 120hz 90 db e n output voltage noise 0.1hz f ? 10hz 1.0 v p-p v n broadband voltage noise 10hz f ? 1khz 1.2 v rms noise density f = 1khz, v in = 9.5v 38 nv/ ? hz ? v out / ? t long term drift t a = +125c, 1000hrs 15 ppm
isl71090seh75 6 fn8591.3 march 18, 2016 submit document feedback electrical specif ications for die v in = 15v, i out = 0ma, c l = 0.1f and c c = 1nf unless otherwise specified. boldface limits apply after radiation a t +25c and across the operating temperature range, -55c to +125 c without radiation, unless otherwise specified. specification s over temperature are guaranteed but not production tested on die. parameter description test conditions min ( note 7 )typ max ( note 7 )unit v out output voltage 7.5 v v oa v out accuracy at t a = +25c v out = 7.5v, ( note 11 ) -0.05 +0.05 % v out accuracy at t a = -55c to +125c v out = 7.5v, ( note 11 ) -0.15 +0.15 % v out accuracy at t a = +25c, post radiation v out = 7.5v, ( note 11 ) -0.3 +0.3 % tc v out output voltage temperature coefficient ( note 8 ) 10 ppm/c v in input voltage range 9.2 30 v i in supply current 0.930 1.500 ma ? v out / ? v in line regulation v in = 9.2v to 30v 8 20 ppm/v ? v out / ? i out load regulation sourcing: 0ma i out 20ma 10 20 ppm/ma sinking: -10ma i out 0ma 21 40 ppm/ma v d dropout voltage ( note 10 ) 1.5 1.7 v notes: 7. compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. 8. over the specified temperature range. temperature coefficien t is measured by the box method whereby the change in v out(max) - v out(min) is divided by the temperature range; in this case, -55c to +125c = +180c. 9. post-reflow drift for the isl71090seh75 devices can be 100v ty pical based on experimental results with devices on fr4 double sided boards. the engineer must take this into account when co nsidering the reference voltage after assembly. 10. dropout voltage is the minimum v in - v out differential voltage measured at the point where v out drops 1mv from v in = nominal at t a = +25c. 11. the v out accuracy is based on die mount with silver glass die attach material such as "qmi 2569" or equivalent in a package with an alu mina ceramic substrate.
isl71090seh75 7 fn8591.3 march 18, 2016 submit document feedback typical performance curves v out = 7.5v, t a = +25c, c out = 1f, comp = 1nf, unless otherwise specified. figure 4. v out accuracy over temperatur e figure 5. line regulation over temperature at v in = 5v (ppm/ma) figure 6. v out vs v in at 0ma, 20ma and -10ma figure 7. load regulation over temperature at v in = 9.2v figure 8. load regulation over temperature at v in = 9.2v (ppm/ma) 7.490 7.492 7.494 7.496 7.498 7.500 7.502 7.504 7.506 7.508 7.510 0 5 10 15 20 25 30 35 v in (v) v out (v) 0ma, +25c v out (v) 0ma, +125c v out (v) 0ma, -55c 7.5v + 0.1% 7.5v - 0.1% v out (v) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0 5 10 15 20 25 30 35 v in (v) line regulation (ppm/v) line reg ppm/v +25c line reg ppm/v m-55c line reg ppm/v +125c 7.490 7.492 7.494 7.496 7.498 7.500 7.502 7.504 7.506 7.508 7.510 0 5 10 15 20 25 30 35 v in (v) v out (v) 7.5v -0.1% 7.5v +0.1% v out (v) 0ma +25c v out (v) 20ma +25c v out (v) -10ma +25c v out (v) 0ma +125c v out (v) 20ma +125c v out (v) -10ma +125c v out (v) 0ma -55c v out (v) 20ma -55c v out (v) -10ma -55c -10 -5 0 5 10 15 20 25 i out (ma) 7.490 7.492 7.494 7.496 7.498 7.500 7.502 7.504 7.506 7.508 7.510 v out (v) 7.5v + 0.1% 7.5v - 0.1% v out (v), +25c v out (v), +125c v out (v), -55c -15 -10 -5 0 5 10 15 20 -10 -5 0 5 10 15 20 25 i out (ma) load regulation (ppm/ma) load reg ppm/ma (v in = 5v, +25c) load reg ppm/ma (v in = 5v, -55c) load reg ppm/ma (v in = 5v, +125c)
isl71090seh75 8 fn8591.3 march 18, 2016 submit document feedback figure 9. dropout voltage for 7.5v figure 10. load transient 0 to 1ma figure 11. noise density vs frequency (v in = 9.5v, v out = 7.5v, i out = 0ma figure 12. v out vs temperature figure 13. psrr (+25c, v in = 9.5v, v out = 7.5v, i out = 0ma, c in = 0.1f, c out = 1.0f, comp = 1nf, v sig = 300mv p-p ) typical performance curves v out = 7.5v, t a = +25c, c out = 1f, comp = 1nf, unless otherwise specified. (continued) 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 0.0 0.005 0.010 0.015 0.020 0.025 i out (a) dropout (v) +25c +150c +125c 100s/div v out v in = 9v v out = 7.5v v out 0ma to 1ma slew rate: 2ma/s c out = 1f comp = 1000pf 20mv/div 1.e-09 1.e-08 1.e-07 1.e-06 1.e-05 0.1 1 10 100 1k 10k 100k frequency (hz) noise (v/hz) f = 1khz v in = 9.5v v out = 7.5v r i = open en = 37.5nv/hz 7.490 7.492 7.494 7.496 7.498 7.500 7.502 7.504 7.506 7.508 7.510 -80 -60 -40 -20 0 20 40 60 80 100 120 140 temperature (c) 7.5v + 0.1% 7.5v - 0.1% unit 1 unit 4 unit 5 unit 2 unit 3 v out (v) -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 10 100 1k 10k 100k 1m frequency (hz) psrr (db)
isl71090seh75 9 fn8591.3 march 18, 2016 submit document feedback device operation bandgap precision reference the isl71090seh75 uses a bandgap architecture and special trimming circuitry to produce a temperature compensated, precision voltage reference with high input voltage capability and moderate output current drive. applications information board mounting considerations for applications requiring the hi ghest accuracy, board mounting location should be reviewed. the device uses a ceramic flatpack package. generally, mild stresses to the die when the printed circuit (pc) board is heated and cooled, can slightly change the shape. because of these die stresse s, placing the device in areas subject to slight twisting can cause degradation of reference voltage accuracy. it is normally be st to place the device near the edge of a board, or on the shortest side, because the axis of bending is most limited in that location. mounting the device in a cutout also minimizes flex. obvi ously, mounting the device on flexprint or extremely thin pc material will likewise cause loss of reference accuracy. board assembly considerations some pc board assembly prec autions are necessary. normal output voltage shifts of typically 100v can be expected with pb-free reflow profiles or wave solder on multilayer fr4 pc boards. precautions should be ta ken to avoid excessive heat or extended exposure to high reflow or wave solder temperatures. noise performance and reduction the output noise voltage over th e 0.1hz to 10hz bandwidth is typically 1.0v p-p (v out = 7.5v). the noise measurement is made with a 9.9hz bandpass filter. noise in the 10hz to 1khz bandwidth is approximately 1.2v rms , with 1f capacitance on the output. this noise measurem ent is made with a bandpass filter of 990hz. load capacitance up to 10f (with comp capacitor listed in table 2 ) can be added but will result in only marginal improvements in output noise and transient response. turn-on time normal turn-on time is typically 250s, the circuit designer must take this into account when l ooking at power-up delays or sequencing. temperature coefficient the limits stated for temperature coefficient (tempco) are governed by the method of measurement. the overwhelming standard for specifying the temperature drift of a reference is to measure the reference voltage at two temperatures, which provide for the maximum voltage deviation and take the total variation, (v high -v low ), this is then divided by the temperature extremes of measurement (t high ?t low ). the result is divided by the nominal reference voltage (at t = +25c) and multiplied by 10 6 to yield ppm/c. this is the ?box? method for specifying temperature coefficient. output voltage adjustment the output voltage can be adjusted above and below the factory-calibrated value via the trim terminal. the trim terminal is the negative feedback divider po int of the output op amp. the voltage at the trim pin is set at approximately 1.216v by the internal bandgap and amplifier circuitry of the voltage reference. the suggested method to adjust the output is to connect a 1m external resistor directly to the trim terminal and connect the other end to the wiper of a potentiometer that has a 100k resistance and whose outer terminals connect to vout and ground. if a 1m resistor is connected to trim, the output adjust range will be 6.3mv. the trim pin should not have any capacitor tied to its output, also it is important to minimize the capacita nce on the trim terminal during layout to preserve output amplifier st ability. it is also best to connect the series resistor directly to the trim terminal to minimize that capacitance and also to minimize noise injection. small trim adjustments will not disturb the factory-set temperature coefficient of the reference, but trimming near the extreme values can. output stage the output stage of the device ha s a push-pull configuration with an high-side pnp and a low-side npn. this helps the device to act as a source and sink. the device can source 20ma. use of comp capacitor the reference can be compensated for the c out capacitors used by adding a capacitor from comp pin to gnd. see table 2 for recommended values. of the comp capacitor. see testing the set result is based on the isl71090seh25. the isl71090seh25 and isl71090seh75 share the same active circuitry consisting of a precisio n bandgap circuit and a trimmable amplifier to set the output referenc e with only a resistor change to scale the output. the set test was done under an ion beam having an let of 86mev?cm 2 /mg. the device did not latch up or burn out to a v dd of 36v and at +125c. sing le event transients were observed and are summarized in the table 3 : dnc pins these pins are for trimming purposes and for factory use only. do not connect these to the circuit in any way. it will adversely effect the performance of the reference. table 2. c out (f) c comp (nf) 0.1 1 11 10 10 table 3. v in (v) i out (ma) c out (f) set (% v out ) 451-4.6 30 5 1 -4.4 30 5 10 -1.0
isl71090seh75 10 fn8591.3 march 18, 2016 submit document feedback package characteristics weight of packaged device 0. 31 grams (typical) lid characteristics finish: gold potential: connected to lead #4 (gnd) case isolation to any lead: 20 x 10 9 (min) die characteristics die dimensions 1464m x 1744m (58 mils x 69 mils) thickness: 483m 25m (19 mils 1 mil) interface materials glassivation type: nitrox thickness: 15k? top metallization type: alcu (99.5%/0.5%) thickness: 30k? backside finish silicon assembly related information substrate potential floating additional information worst case current density <2 x 10 5 a/cm 2 process dielectrically isolated advanced bipolar technology- pr40 soi metallization mask layout gnd gnd powr quiet comp vs dnc dnc dnc vout sense vout force trim (see note 12 , table 4 )
isl71090seh75 11 fn8591.3 march 18, 2016 submit document feedback table 4. die layout x-y coordinates pad name pad number x (m) y (m) bond wires per pad gnd pwr 2 -104 0 1 gnd quiet 1 0 0 1 comp 3 -108 589 1 vs 4 -125 1350 1 dnc 5 -108 1452 1 dnc 6 1089 1452 1 dnc 7 1089 1350 1 vout sense 8 1072 598 1 vout force 9 1088 1 1 trim 10 985 -25 1 notes: 12. origin of coordinates is the centroid of gnd quiet. 13. bond wire size is 1.0 mil.
isl71090seh75 12 intersil products are manufactured, assembled and tested utilizing iso9001 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn8591.3 march 18, 2016 for additional products, see www.intersil.com/en/products.html submit document feedback about intersil intersil corporation is a leading provider of innovative power ma nagement and precision analog so lutions. the company's product s address some of the largest markets within the industrial and infrastr ucture, mobile computing and high-end consumer markets. for the most updated datasheet, application notes, related docu mentation and related parts, please see the respective product information page found at www.intersil.com . you may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask . reliability reports are also av ailable from our website at www.intersil.com/support . revision history the revision history provided is for informational purposes only and is believed to be accurate, but not warranted. please go to the web to make sure that you have the latest revision. date revision change march 18, 2016 fn8591.3 -changed title from ?radiation hardened ultra low noise, precision voltage reference? to ?7.5v radiation hardened ultra low nois e, precision voltage reference? -updated related literature document titles to match titles on the actual documents. -added table 1 to page 2. -corrected the evaluation board part number in the ordering information table on page 2. -on page 5: -changed electrical specification for flatpack no te from: "boldface limits apply over the operating temperature range, -55c to +125c and radiation. ? to: "boldface limits apply after radiation at +25c or across the operating temperature rang e, -55c to +125c without radiation, unless otherwise specified. -for parameter voa (row 4) in electrical specifications for flatpack table changed description from: "vout accuracy, post rad", to: "vout accuracy at ta = +25c, post radiation? and for parameters voa (rows 2, 3, 4) added "not e 9" to conditions column. -on page 6: -changed electrical specification for die note from: "boldface limits apply over the operating temperature range, -55c to +125c and radiation. " to: "boldface limits apply after radiation at +25c or across the operating temperature rang e, -55c to +125c without radiation, unless otherwise specified. -for parameter voa (row 4) in electrical specific ations for die table changed description from: "vout accuracy, post rad", to: "vout accuracy at ta = +25c, post radiation? and for parameters voa for post radiation (row 4) added "note 11" to conditions column. -updated pod k8.a to the latest revision changes are as follows: modified note 2 by adding the words ?...in addition to or instead of...? december 2, 2013 fn8591.2 electrical spec tabl e on page 5 (flatpack) and page 6 (die): v out accuracy post rad section, changed the value for min from -0.25% to -0.3% and max from +0.25% to +0.3%. october 4, 2013 fn8591.1 initial release.
isl71090seh75 13 fn8591.3 march 18, 2016 submit document feedback package outline drawing k8.a 8 lead ceramic metal seal flatpack package rev 4, 12/14 lead finish side view top view -d- -c- 0.265 (6.75) 0.110 (2.79) 0.026 (0.66) 0.265 (6.73) seating and 0.180 (4.57) 0.03 (0.76) min base plane -h- 0.009 (0.23) 0.005 (0.13) pin no. 1 id area 0.050 (1.27 bsc) 0.022 (0.56) 0.015 (0.38) min 0.245 (6.22) 0.087 (2.21) 0.170 (4.32) 0.370 (9.40) 0.325 (8.26) 0.004 (0.10) 0.245 (6.22) 1. adjacent to pin one and shall be located within the shaded area shown. the manufacturers identification shall not be used as a pin on e identification mark. alternately, a tab may be used to identify pin one. 2. 3. the maximum limits of lead dimensions (section a-a) shall be measured at the centroid of the finished lead surfaces, when so lder dip or tin plate lead finish is applied. 4. 5. shall be molded to the bottom of the package to cover the leads . 6. meniscus) of the lead from the body. dimension minimum shall be reduced by 0.0015 inch (0. 038mm) maximum when solder dip lead finish is applied. 7. 8. notes: 0.015 (0.38) 0.008 (0.20) pin no. 1 id optional 1 2 4 6 3 dimensioning and tolerancing per ansi y14.5m - 1982. controlling dimension: inch. index area: a notch or a pin one identification mark shall be l ocated if a pin one identification mark is used in addition to or inst ead of a tab, measure dimension at all four corners. for bottom-brazed lead packages, no organic or polymeric materi als dimension shall be measured at the point of exit (beyond the section a-a base metal 0.007 (0.18) 0.004 (0.10) 0.009 (0.23) 0.004 (0.10) 0.019 (0.48) 0.015 (0.38) 0.0015 (0.04) max 0.022 (0.56) 0.015 (0.38) 0.036 (0.92) the limits of the tab dimension do not apply.

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